How a silicon wafer becomes a computer chip

A computer chip contains huge numbers of switches, yet making each one is not simply a matter of drawing a smaller line. The wafer must be clean, the layers uniform, the patterns aligned and the finished devices connected. Each improvement changes the constraints on the next step.

In this 2012 talk, Todd Fernandez, a mechanical engineer who says he worked in four semiconductor fabs, takes the audience from a transistor cross-section to a finished chip. The credited YouTube channel is Andor Gafotas; Fernandez is the speaker. His examples describe technology and expectations of that period. In particular, the later forecasts should be read as a historical snapshot, not a current industry roadmap. Watch from 02:08

For scale, Fernandez compares a roughly 40-micrometre human hair with historical feature sizes: 10 micrometres for the 1971 Intel 4004 and 32 nanometres around 2010. These are illustrative comparisons, not interchangeable definitions of modern process nodes.

Start with a silicon wafer, the substrate on which devices are built. Two regions, the source and drain, are made electrically different by adding small amounts of impurities called dopants. Between them lies a channel. Above it, an insulating gate dielectric separates the silicon from the gate. Applying a voltage to the gate creates an electric field that controls whether current can flow through the channel.

Fernandez uses this structure to explain why digital hardware is built from analog devices. A transistor does not jump perfectly between zero and one: its current changes with gate voltage, and even an “off” transistor can leak. The threshold voltage marks the region where it begins to turn on. Less leakage reduces wasted power and heat; a sharper transition makes the two states easier to distinguish. Watch from 03:08

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A fab is a multi-level factory built around exceptionally clean manufacturing space. Fernandez gives a period example of roughly 300,000 square feet and a class-one cleanroom, contrasted with his class-10,000 operating-room comparison. These are examples from his talk, not specifications for every factory.

Wafers begin as single-crystal silicon ingots grown in a furnace and sliced into discs. The crystal's orderly arrangement matters to subsequent processing; contamination matters because a particle can dwarf a feature being made. In his 2012 account, 300 mm wafers were standard at leading facilities, while 450 mm wafers were being developed.

The wafers travel in front-opening unified pods, or FOUPs: enclosed carriers moved by automated equipment. Even a cleanroom may not be clean enough at the wafer surface, and carriers can be separated by process stage to limit cross-contamination. A video of a mishandled wafer illustrates the stakes. Fernandez estimates potential revenue of $60,000 per leading-edge wafer, but his explanation of the apparent robot misalignment and suggestion that these were test wafers are informed guesses, not established details of the incident. Watch from 07:12

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Photolithography transfers a pattern to a light-sensitive coating called photoresist. A track coats and develops the wafer; a stepper or scanner projects a pattern from a mask onto it. That pattern guides later material removal or modification. Fernandez describes a then-current tool costing about $35 million and taking 18 months to obtain, emphasizing that precision and equipment availability both constrain production.

His example uses 193-nanometre light to make smaller features. A mask shaped exactly like the desired feature will not necessarily print that shape. Optical proximity correction deliberately changes the mask geometry so that the optical system produces a closer approximation on the wafer. Anti-reflective coatings also manage reflections that otherwise distort the resist profile.

Immersion lithography adds a controlled volume of very clean water between lens and wafer. Water's refractive index improves the achievable resolution with the same light. Rather than dipping a moving wafer into a bath, supply and recovery systems maintain a local water volume under the lens. Fernandez also introduces extreme ultraviolet (EUV) lithography as a difficult prospective technology: his doubts about its feasibility and timing reflect 2012, not a present-day assessment. Watch from 11:16

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Ion implantation puts dopants into selected regions. Fernandez compares the tool to a small particle accelerator: ions are accelerated toward the wafer and embedded in its surface. Different doses and locations help create the source and drain and tune the device.

Deposition builds material up. In chemical vapor deposition, gases react at the wafer surface to form a layer. Uniformity across the disc matters: a layer that varies in thickness can produce transistors with different behavior at different locations.

Atomic layer deposition alternates precursor exposures and removes the intervening gases and byproducts. Repeating the cycle offers fine thickness control and produces conformal coatings: layers that follow the walls of tall, narrow features. The chemistry must work for the material and surface involved; Fernandez's comments about specific materials he believed unavailable are explicitly qualified and belong to the period of the talk. Watch from 18:44

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Fernandez's simplified sequence starts with shallow trench isolation: insulating trenches separate neighboring devices to limit leakage and unwanted interaction. A gate insulator and gate material are formed, followed by light implants for the source and drain. Spacers alongside the gate narrow the openings for heavier implants, helping shape the dopant profile.

A self-aligned silicide, or salicide, helps make electrical contact to the silicon regions. A short, high-temperature treatment redistributes dopants. An insulating layer then covers the device; openings are etched and filled with metal to form contacts. Above these, successive metal layers connect transistors into logic, memory and larger circuits. Fernandez compares the device to a house, its contact to a driveway and the upper interconnects to progressively larger roads.

The drawing makes the process look like a handful of operations, but each box hides many steps. He estimates around 500 operations and three weeks to reach backend processing in his example; isolation trenches alone require at least 13 physical actions, excluding inspection. These are illustrative estimates, not a recipe for every chip. Watch from 27:53

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Fernandez zooms from a device cross-section down to a 2010-era gate insulator: about 1.2 nanometres of silicon dioxide, which he describes as four atomic layers. At that scale, controlling even a layer's variation becomes consequential. He distinguishes the quoted switching speed of a transistor from the clock speed of the chip and says he is unsure about the paper's reported clock figure.

Zooming back out shows the devices at the bottom and many layers of interconnect above. The transistors are only one part of the manufactured stack; the wiring gives them a way to work together. Watch from 33:12

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The goal is to make the off state leak less, make the transition sharper and, where possible, turn on at a lower voltage. These properties interact: improving one may allow engineers to retune the others for speed and energy.

Strained silicon changes the spacing of atoms by stretching or compressing the crystal, changing how readily charge carriers move. Fernandez cites a 35% speed improvement for one design change, while noting that implementing it required many manufacturing steps and that leakage must also be managed.

A high-k gate dielectric provides the desired electrical behavior with a physically thicker insulator than an extremely thin silicon-dioxide layer. Metal gates can reduce resistance compared with polysilicon, but the materials can be sensitive to later high-temperature processing. In a gate-last approach, a temporary gate defines the structure and is later removed; the final dielectric and metal fill its narrow opening. Filling that space without voids is difficult, which makes conformal deposition valuable. Watch from 36:57

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A fully depleted structure uses a controlled thin semiconductor layer above an insulator. Together with side isolation, the underlying insulator helps limit unwanted paths beneath the device. Fernandez likens the isolation to a Faraday cage but explicitly says it is an analogy, not a literal cage.

A FinFET raises the channel into a narrow fin and places the gate around three sides instead of only above a flat surface. That geometry gives the gate better control over the channel. Multiple fins can be connected to provide different drive capabilities. The presentation cites 50% lower power and 40% higher speed for a particular period comparison; these figures are not universal guarantees. Fernandez also stresses the manufacturing difficulty and says he does not know Intel's exact process. Watch from 44:16

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Fernandez presents gate-all-around devices, larger wafers, multiple patterning, EUV and new interconnects as possible directions. He explicitly calls his own explanation of double patterning poor, so it should not be used as a technical definition. He also describes resist outgassing in a vacuum as an EUV challenge and discusses optical interconnects and experimental atomic-scale devices. These are the speaker's historical proposals and concerns; the dates and feasibility claims are not a verified account of what later happened. Watch from 48:57

In questions, Fernandez describes Moore's law in terms of density and price, predicting in 2012 that cost would become a limiting problem within about a decade. He also discusses radiation-related errors and mitigation through circuit design, software and error checking; the talk's specific attribution to neutrinos is uncertain. Dopants can diffuse over time, especially with heat, and he suggests device design and replacement cycles affect the practical impact.

On rising research costs, he expects consolidation among manufacturers but points to specialized atomic-layer-deposition suppliers as a source of innovation. He disclaims expertise in economics. Asked about focused ion beams, he finds the technique interesting but does not know how to make it practical for manufacturing. The common theme is that a working laboratory idea still has to become a repeatable, reliable and economical factory process. Watch from 54:11